1. Technical Field
The present invention relates generally to a method for managing cache line replication in multi-core integrated circuits components (chips). More particularly, the present invention relates to a method for a flexible replication with skewed mapping in a multi-core chip.
2. Description of the Related Art
Data processing systems include processors for performing computations. A processor can include multiple processing cores. A core is a processor or a unit of a processor circuitry that is capable of operating as a separate processing unit. A core includes the processor circuitry as well as data storage, such as a level 1 cache (L1) and a level 2 cache (L2). Some data processing systems can include multiple processors.
A single chip including multiple cores thereon is called a multi-core chip. In a multi-core chip, one core may request a cache line from another core in a process called cache line replication (replication). A block of data in a cache of a core is called a cache line.